The direction of sophisticated computer systems is toward virtual memory configurations based on demand paged physical memory. Paging, in this context, means the subdivision of physical memory into equal sized blocks called page frames. The Logical Address space of a task is then divided into pages which have the same number of bytes as the page frames. This division is invisible to the user tasks, but the operating system is aware of it and controls the allocation of pages to page frames. This is a desirable method for memory allocation since all of the code and data segments (consisting of many pages) do not need to be resident in physical memory. Only those pages that are currently being used by the process need to be assigned to page frames.
The term "demand" means that a process does not need to specify in advance what areas of its logical address space it requires. An access to a Logical Address is interpreted by the system as a request to load that memory. In a demand paged system, pages are loaded into page frames by the operating system when the process addresses them. This requires a processor with a virtual memory capability, such as the processor described in U.S. Pat. No. 4,488,228.
In such systems, all accesses by the processor to the paged memory are managed by a paged memory management unit (PMMU). In general, the primary responsibility of the PMMU is to translate Logical Addresses provided by the processor to the appropriate Physical Addresses required by the memory. Typically, the mapping between Logical and Physical Addresses is defined by a translation table in the memory. The PMMU becomes bus master to access this table without the assistance of the processor.
In order to avoid consulting the translation table on every bus cycle, the PMMU preferably contains a cache of recently used translations. This cache is typically a multiple entry Content Addressable Memory (CAM). On each processor bus cycle, the Logical Address is checked against the entries in this cache. If a matching entry is found, the Physical Address is output immediately. Otherwise, the PMMU must abort the bus cycle so that access may be made to the translation table. Once the bus becomes available, the PMMU "walks" the translation table to determine the correct translation. After the translation has been completed, the cache is updated to reflect the new translation. Typically, if the cache is full, an older entry, such as the least recently used entry, is replaced with the new entry. As soon as the PMMU releases the bus, the processor can retry the previously-aborted bus cycle. Since the correct entry is now in the cache, the PMMU can provide the appropriate Physical Address and the access can proceed.
Data processing systems having paged memory management units or the like which perform Logical-to-Physical address translation using one or more translation tables stored in main memory are disclosed in the following U.S. Pat. Nos. 3,902,164; 4,037,209; 4,096,573; 4,279,014; 4,355,355; and 4,430,705. Data processing systems having paged memory management units or the like which perform Logical-to-Physical address translation using one or more translation tables stored in special memory or registers are disclosed in the following U.S. Pat. Nos. 4,084,226; 4,296,468; 4,395,754.